1. Field of the Invention
The present invention relates to an apparatus for tuning an RAS (Row Address Strobe) active time in a memory device, and more particularly to an apparatus for tuning a RAS active time in a memory device which can constantly tune the RAS active time by comparing the RAS active time generated in synchronization with a clock signal with the RAS active signal generated through an inverter delay circuit and adjusting a delay time by feeding back the result of comparison.
2. Description of the Prior Art
As generally known in the art, a read operation of a semiconductor memory device is initiated by applying a row active command for activating memory cells, and in a conventional volatile memory device, the row active operation is performed by enabling a /RAS signal to be a low level.
If the /RAS signal is enabled to a low level (in the case of an SDRAM, if the corresponding command is applied), DRAM reads data stored in the memory cells, restores the same data as the read data in the memory cells, and then becomes pre-charged.
However, if the pre-charging is performed too fast, a problem may occur in the process of restoring the data in the memory cells. In order to prevent this, a RAS active time tRAS should be secured.
Generally, an inverter delay element is used to secure the RAS active time tRAS. However, the delay time of such an inverter delay element varies according to the temperature characteristic or voltage characteristic of the element. Accordingly, in the case of using the inverter delay element, the RAS active time tRAS is not fixed, but is changed.
Although a method for reflecting a result obtained from a specified test on an adjustment option for the inverter delay element may be proposed in order to solve the problem that the RAS active time tRAS is changed, it is difficult to set a proper RAS active time and the RAS active time is dependent on the characteristic of the element.